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| author | Stefan Agner <[email protected]> | 2016-12-14 20:48:09 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-03-10 01:10:49 +0000 |
| commit | 53990e416bb7adaa59d045f325a47f31a11b75ee (patch) | |
| tree | d87ea97b09ecedad96ffaf192c35dc1ee616517f /drivers/gpu/drm/tilcdc | |
| parent | drm: mxsfb: use bus_format to determine LCD bus width (diff) | |
| download | kernel-53990e416bb7adaa59d045f325a47f31a11b75ee.tar.gz kernel-53990e416bb7adaa59d045f325a47f31a11b75ee.zip | |
drm: mxsfb: fix pixel clock polarity
The DRM subsystem specifies the pixel clock polarity from a
controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
the controller drives the data on pixel clocks falling edge.
That is the controllers DOTCLK_POL=0 (Default is data launched
at negative edge).
Also change the data enable logic to be high active by default
and only change if explicitly requested via bus_flags. With
that defaults are:
- Data enable: high active
- Pixel clock polarity: controller drives data on negative edge
Signed-off-by: Stefan Agner <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/tilcdc')
0 files changed, 0 insertions, 0 deletions