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| author | Tirumalesh Chalamarla <[email protected]> | 2016-02-04 18:45:25 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2016-02-11 10:20:02 +0000 |
| commit | 1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596 (patch) | |
| tree | 5a046e3c634ce678ac7c73e2293bc485024e8eb1 /drivers/gpu/drm/omapdrm/omap_gem.c | |
| parent | irqchip/gic: Only set the EOImodeNS bit for the root controller (diff) | |
| download | kernel-1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596.tar.gz kernel-1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596.zip | |
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:
4.1.1 Physical CPU Interface:
The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
on the state of a returned INTID are not guaranteed
to be visible until after the execution of a DSB.
Not having this could result in missed interrupts, so let's add the
required barrier.
[Marc: fixed commit message]
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Tirumalesh Chalamarla <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_gem.c')
0 files changed, 0 insertions, 0 deletions