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| author | Clint Taylor <[email protected]> | 2018-12-17 22:13:47 +0000 |
|---|---|---|
| committer | Imre Deak <[email protected]> | 2018-12-18 14:00:16 +0000 |
| commit | b265a2a6255f581258ccfdccbd2efca51a142fe2 (patch) | |
| tree | ca6c18e330f342c3a92cfca69a75a4e16c5cc503 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Update crtc scaler settings when update_pipe is set (diff) | |
| download | kernel-b265a2a6255f581258ccfdccbd2efca51a142fe2.tar.gz kernel-b265a2a6255f581258ccfdccbd2efca51a142fe2.zip | |
drm/i915/icl: combo port vswing programming changes per BSPEC
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
v5: Misc review comments + r-b
BSpec: 21257
Cc: Ville Syrjälä <[email protected]>
Cc: Imre Deak <[email protected]>
Cc: Rodrigo Vivi <[email protected]>
Reviewed-by: Imre Deak <[email protected]>
Signed-off-by: Clint Taylor <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions