diff options
| author | Lucas De Marchi <[email protected]> | 2018-12-12 18:10:42 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2018-12-13 00:51:49 +0000 |
| commit | 006900087727f675e9367eb3c3e054912ddbffdd (patch) | |
| tree | 470c1a2174f67bc7ee95be0b4a62e2bfa3529530 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Don't forget to reset blocks when testing lower wm levels (diff) | |
| download | kernel-006900087727f675e9367eb3c3e054912ddbffdd.tar.gz kernel-006900087727f675e9367eb3c3e054912ddbffdd.zip | |
drm/i915: Rename IS_GEN to IS_GEN_RANGE
RANGE makes it longer, but clearer. We are also going to add a macro to
check an individual gen, so add the _RANGE prefix here.
Diff generated with:
sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/{*/,}*.{c,h} -i
v2: use IS_GEN rather than GT_GEN
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Tvrtko Ursulin <[email protected]>
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 02f6a9b81083..720c11e0acd1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -445,7 +445,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) POSTING_READ(mmio); /* Flush the TLB for this page */ - if (IS_GEN(dev_priv, 6, 7)) { + if (IS_GEN_RANGE(dev_priv, 6, 7)) { i915_reg_t reg = RING_INSTPM(engine->mmio_base); /* ring should be idle before issuing a sync flush*/ @@ -679,7 +679,7 @@ static int init_render_ring(struct intel_engine_cs *engine) return ret; /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - if (IS_GEN(dev_priv, 4, 6)) + if (IS_GEN_RANGE(dev_priv, 4, 6)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order @@ -688,7 +688,7 @@ static int init_render_ring(struct intel_engine_cs *engine) * * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv */ - if (IS_GEN(dev_priv, 6, 7)) + if (IS_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); /* Required for the hardware to program scanline values for waiting */ @@ -713,7 +713,7 @@ static int init_render_ring(struct intel_engine_cs *engine) _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); } - if (IS_GEN(dev_priv, 6, 7)) + if (IS_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); if (INTEL_GEN(dev_priv) >= 6) |