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| author | Chris Wilson <[email protected]> | 2017-02-25 18:11:22 +0000 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2017-02-25 18:54:38 +0000 |
| commit | 9e89f9ee3b16cca56bed5fa45e63f422d3ac2c3a (patch) | |
| tree | bc7ad5c7c8df635166295cbc3b72ef360d9e601a /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | drm/i915: Sanity check the vma->node prior to binding into the GTT (diff) | |
| download | kernel-9e89f9ee3b16cca56bed5fa45e63f422d3ac2c3a.tar.gz kernel-9e89f9ee3b16cca56bed5fa45e63f422d3ac2c3a.zip | |
drm/i915: Advance start address on crossing PML (48b ppgtt) boundary
When advancing onto the next 4th level page table entry, we need to
reset our indices to 0. Currently we restart from the original address
which means we start with an offset into the next PML table.
Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
Reported-by: Matthew Auld <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99948
Testcase: igt/drv_selftest/live_gtt
Signed-off-by: Chris Wilson <[email protected]>
Cc: Matthew Auld <[email protected]>
Tested-by: Matthew Auld <[email protected]>
Reviewed-by: Matthew Auld <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions