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| author | Ankit Nautiyal <[email protected]> | 2025-03-24 13:32:34 +0000 |
|---|---|---|
| committer | Ankit Nautiyal <[email protected]> | 2025-03-25 15:45:55 +0000 |
| commit | 5e25f996be596800c0d8ba0df46ffacd6cae9fc8 (patch) | |
| tree | 5246d6aa61a4c69eef8be5ef5de9eb9e5b85c996 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/hdmi: Use VRR Timing generator for HDMI for fixed_rr (diff) | |
| download | kernel-5e25f996be596800c0d8ba0df46ffacd6cae9fc8.tar.gz kernel-5e25f996be596800c0d8ba0df46ffacd6cae9fc8.zip | |
drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rr
Currently the variable timings are supported only for DP and eDP and not
for DP MST. Call intel_vrr_compute_config() for MST which will configure
fixed refresh rate timings irrespective of whether VRR is supported or
not. Since vrr_capable still doesn't have support for DP MST this will be
just treated as non VRR case and vrr.vmin/vmax/flipline will be all set
to adjusted_mode->crtc_vtotal.
This will help to move away from the legacy timing generator and
always use VRR timing generator by default.
With this change, we need to exclude MST in intel_vrr_is_capable for
now, to avoid having LRR with MST.
v2: Exclude MST in intel_vrr_is_capable() for now. (Ville)
Signed-off-by: Ankit Nautiyal <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 02f95108c637..bd47cf127b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -52,6 +52,7 @@ #include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #include "skl_scaler.h" /* @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state); intel_ddi_compute_min_voltage_level(pipe_config); |