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| author | Dave Airlie <[email protected]> | 2022-01-20 22:31:29 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2022-01-20 22:31:29 +0000 |
| commit | 410482b51afecddb8fc29324d1b11945dfa0b682 (patch) | |
| tree | a151b9aff2e939706221f526543c6d6f017900e9 /drivers/gpu/drm/i915/display/intel_ddi.c | |
| parent | Merge tag 'amd-drm-next-5.17-2022-01-12' of https://gitlab.freedesktop.org/ag... (diff) | |
| parent | drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence (diff) | |
| download | kernel-410482b51afecddb8fc29324d1b11945dfa0b682.tar.gz kernel-410482b51afecddb8fc29324d1b11945dfa0b682.zip | |
Merge tag 'drm-intel-next-fixes-2022-01-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Latest updates for the EHL display voltage swing table (José Roberto de Souza)
- Additional step is required when programming the ADL-P display TC voltage swing (José Roberto de Souza)
Signed-off-by: Dave Airlie <[email protected]>
From: Tvrtko Ursulin <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/Yek1zdsnRPiBVvFF@tursulin-mobl2
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9c9d574f0b8c..cab505277595 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1298,6 +1298,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), DKL_TX_DP20BITMODE, 0); + + if (IS_ALDERLAKE_P(dev_priv)) { + u32 val; + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { + if (ln == 0) { + val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); + val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); + } else { + val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); + val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); + } + } else { + val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); + val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); + } + + intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, + val); + } } } |