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authorCristian Ciocaltea <[email protected]>2025-02-04 12:40:04 +0000
committerHeiko Stuebner <[email protected]>2025-02-06 10:57:52 +0000
commit79982cbac896768c3860c241df2028c3e75f5a6b (patch)
treefe837eecdc1c1056d9843881d36c69a59423e6bf /drivers/gpu/drm/display/drm_dp_mst_topology.c
parentdt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588 HDMI TX... (diff)
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dt-bindings: display: vop2: Add optional PLL clock properties
On RK3588, HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 video ports 0, 1 and 2. Document the optional PLL clock properties corresponding to the two HDMI PHYs available on the SoC. Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Tested-by: FUKAUMI Naoki <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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