diff options
| author | Ilya Bakoulin <[email protected]> | 2025-06-18 17:07:14 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-06-30 15:58:55 +0000 |
| commit | 660a467a5e7366cd6642de61f1aaeaf0d253ee68 (patch) | |
| tree | 32cb06ebdcb64fc588dec270153560e7ed4578ef /drivers/gpu/drm/amd/display | |
| parent | drm/amd/display: Refactor DML21 Initialization and Configuration (diff) | |
| download | kernel-660a467a5e7366cd6642de61f1aaeaf0d253ee68.tar.gz kernel-660a467a5e7366cd6642de61f1aaeaf0d253ee68.zip | |
drm/amd/display: Separate set_gsl from set_gsl_source_select
[Why/How]
Separate the checks for set_gsl and set_gsl_source_select, since
source_select may not be implemented/necessary.
Reviewed-by: Nevenko Stupar <[email protected]>
Signed-off-by: Ilya Bakoulin <[email protected]>
Signed-off-by: Ray Wu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 7f9b6c4bf889..3207addbd4eb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -283,14 +283,13 @@ void dcn20_setup_gsl_group_as_lock( } /* at this point we want to program whether it's to enable or disable */ - if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && - pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { + if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { pipe_ctx->stream_res.tg->funcs->set_gsl( pipe_ctx->stream_res.tg, &gsl); - - pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( - pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); + if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) + pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( + pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); } else BREAK_TO_DEBUGGER(); } |