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| author | Paul Burton <[email protected]> | 2019-04-30 22:53:31 +0000 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2019-05-02 18:20:59 +0000 |
| commit | 783454e2bc7ce491b5cd50154433cde993bfd849 (patch) | |
| tree | 3b8906fb5290e2a80dfefa92f5b5ccb3e70d2299 /drivers/gpu/drm/amd/display/modules/freesync | |
| parent | MIPS: Always allocate exception vector for MIPSr2+ (diff) | |
| download | kernel-783454e2bc7ce491b5cd50154433cde993bfd849.tar.gz kernel-783454e2bc7ce491b5cd50154433cde993bfd849.zip | |
MIPS: Sync icache for whole exception vector
Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
Tested-by: Serge Semin <[email protected]>
Cc: [email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync')
0 files changed, 0 insertions, 0 deletions