diff options
| author | George Shen <[email protected]> | 2024-06-17 20:32:15 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-07-01 20:06:53 +0000 |
| commit | 95134e5852978a92d2290a3b1ee93189e75507ac (patch) | |
| tree | 9b5df7fbb7101ba1c901c25de1cc73d24c78c7c6 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0 (diff) | |
| download | kernel-95134e5852978a92d2290a3b1ee93189e75507ac.tar.gz kernel-95134e5852978a92d2290a3b1ee93189e75507ac.zip | |
drm/amd/display: Add ASIC cap to limit DCC surface width
[Why]
Certain configurations of DCN401 require ODM4:1 to support DCC for 10K
surfaces. DCC should be conservatively disabled in those cases.
The issue is that current logic limits 10K surface DCC for all
configurations of DCN401.
[How]
Add DC ASIC cap to indicate max surface width that can support DCC.
Disable DCC if this ASIC cap is non-zero and surface width exceeds it.
Reviewed-by: Jun Lei <[email protected]>
Signed-off-by: Jerry Zuo <[email protected]>
Signed-off-by: George Shen <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions