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| author | Reza Amini <[email protected]> | 2020-07-15 15:33:23 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-08-06 20:40:18 +0000 |
| commit | 471c1dd9546df81d259664ac3e2ab0e99169f755 (patch) | |
| tree | 9c7dfcbbaeedbe03a8cd923733a09745e289d774 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | drm/amd/display: Disable idle optimizations before programming DCN (diff) | |
| download | kernel-471c1dd9546df81d259664ac3e2ab0e99169f755.tar.gz kernel-471c1dd9546df81d259664ac3e2ab0e99169f755.zip | |
drm/amd/display: Allow asic specific FSFT timing optimization
[Why]
Each asic can optimize best based on its capabilities
[How]
Optimizing timing for a new pixel clock
Signed-off-by: Reza Amini <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 7a2500fbf3f2..81820f3d6b3b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -829,10 +829,13 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, switch (packet_type) { case PACKET_TYPE_FS_V3: #ifndef TRIM_FSFT + // always populate with pixel rate. build_vrr_infopacket_v3( stream->signal, vrr, stream->timing.flags.FAST_TRANSPORT, - stream->timing.fast_transport_output_rate_100hz, + (stream->timing.flags.FAST_TRANSPORT) ? + stream->timing.fast_transport_output_rate_100hz : + stream->timing.pix_clk_100hz, app_tf, infopacket); #else build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket); |