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| author | Martin Leung <[email protected]> | 2019-02-13 22:06:31 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-03-19 20:04:03 +0000 |
| commit | 162f807858d15bde60cf373a3ad46e03200ad9d8 (patch) | |
| tree | 521391cd7cd8ee5a7e57b6d50e80516daa873fd9 /drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | |
| parent | drm/amd/display: Keep clocks high before seamless boot done (diff) | |
| download | kernel-162f807858d15bde60cf373a3ad46e03200ad9d8.tar.gz kernel-162f807858d15bde60cf373a3ad46e03200ad9d8.zip | |
drm/amd/display: half bandwidth for YCbCr420 during validation
[Why]
used to be unable to run 4:2:0 if using a dongle because 4k60 bandwidth
exceeded dongle caps
[How]
half pixel clock during comparison to dongle cap. *Could get stuck on black
screen on monitor that don't support 420 but will be selecting 420 as
preferred mode*
Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Aidan Wood <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h')
0 files changed, 0 insertions, 0 deletions