diff options
| author | Roman Li <[email protected]> | 2025-04-03 17:49:03 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-04-21 15:28:30 +0000 |
| commit | e15d09f510d0303b53e556a73fa4236744c19695 (patch) | |
| tree | 57463f646777234a3f6e8c8b69404a1bd75b61c6 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | drm/amd/display: Enable urgent latency adjustment on DCN35 (diff) | |
| download | kernel-e15d09f510d0303b53e556a73fa4236744c19695.tar.gz kernel-e15d09f510d0303b53e556a73fa4236744c19695.zip | |
drm/amd/display: enable phy-ssc reduction by default
[Why]
Reduction of phy-ssc is needed to support DP2 high pixel clock on dcn35x/36.
There's a special flag to enable it in dmub hw params.
[How]
Set hbr3_phy_ssc to true for dcn35, dcn351 and dcn36.
Reviewed-by: Charlene Liu <[email protected]>
Signed-off-by: Roman Li <[email protected]>
Signed-off-by: Zaeem Mohamed <[email protected]>
Tested-by: Mark Broadworth <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e700b1edac2c..aa42be3d63b0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1330,6 +1330,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; + hw_params.lower_hbr3_phy_ssc = true; break; default: break; |