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| author | Brendan Tam <[email protected]> | 2025-03-14 17:09:13 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-03-26 21:43:25 +0000 |
| commit | 8058061ed9d6bc259d1e678607b07d259342c08f (patch) | |
| tree | 7841f629048a57dde5230767da6ad289171b0770 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | Revert "drm/amd/display: dml2 soc dscclk use DPM table clk setting" (diff) | |
| download | kernel-8058061ed9d6bc259d1e678607b07d259342c08f.tar.gz kernel-8058061ed9d6bc259d1e678607b07d259342c08f.zip | |
drm/amd/display: prevent hang on link training fail
[Why]
When link training fails, the phy clock will be disabled. However, in
enable_streams, it is assumed that link training succeeded and the
mux selects the phy clock, causing a hang when a register write is made.
[How]
When enable_stream is hit, check if link training failed. If it did, fall
back to the ref clock to avoid a hang and keep the system in a recoverable
state.
Reviewed-by: Dillon Varone <[email protected]>
Signed-off-by: Brendan Tam <[email protected]>
Signed-off-by: Aurabindo Pillai <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
0 files changed, 0 insertions, 0 deletions