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authorRex Zhu <[email protected]>2016-10-12 12:05:03 +0000
committerAlex Deucher <[email protected]>2016-10-25 18:38:49 +0000
commitdb82b67c5764c02ced886ca2c8c61a7b00b53075 (patch)
treeb63ebca27c39400ead9ec892017fd84e4af6a612 /drivers/gpu/drm/amd/amdgpu
parentdrm/amd/amdgpu: Put in rest of wave fields (diff)
downloadkernel-db82b67c5764c02ced886ca2c8c61a7b00b53075.tar.gz
kernel-db82b67c5764c02ced886ca2c8c61a7b00b53075.zip
drm/amdgpu: check min clock set by DAL before set ps.
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 885f08c3f496..68fe70eda5ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -960,6 +960,12 @@ static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
sclk = ps->performance_levels[0].sclk;
}
+ if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
+ sclk = adev->pm.pm_display_cfg.min_core_set_clock;
+
+ if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
+ mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
+
if (rps->vce_active) {
if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;