diff options
| author | Shashank Sharma <[email protected]> | 2024-06-03 09:13:03 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-04-08 20:48:18 +0000 |
| commit | 30e4d781385dda92fdee574b0a95094dfa143b52 (patch) | |
| tree | 7927a34a40fe504ca18da64e0239a19380ce86e6 /drivers/gpu/drm/amd/amdgpu | |
| parent | drm/amdgpu: add gfx eviction fence helpers (diff) | |
| download | kernel-30e4d781385dda92fdee574b0a95094dfa143b52.tar.gz kernel-30e4d781385dda92fdee574b0a95094dfa143b52.zip | |
drm/amdgpu: add userqueue suspend/resume functions
This patch adds userqueue suspend/resume functions at
core MES V11 IP level.
V2: use true/false for queue_active status (Christian)
added Christian's R-B
V3: reset/set queue status in mqd.create and mqd.destroy
Cc: Alex Deucher <[email protected]>
Cc: Christian Koenig <[email protected]>
Reviewed-by: Christian Koenig <[email protected]>
Signed-off-by: Shashank Sharma <[email protected]>
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c index fe4efe5ba6ac..ee0a757fcfa3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c @@ -331,6 +331,7 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_ctx; } + queue->queue_active = true; return 0; free_ctx: @@ -354,9 +355,41 @@ mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj); kfree(queue->userq_prop); amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd); + queue->queue_active = false; +} + +static int mes_v11_0_userq_suspend(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + if (queue->queue_active) { + mes_v11_0_userq_unmap(uq_mgr, queue); + queue->queue_active = false; + } + + return 0; +} + +static int mes_v11_0_userq_resume(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + int ret; + + if (queue->queue_active) + return 0; + + ret = mes_v11_0_userq_map(uq_mgr, queue, queue->userq_prop); + if (ret) { + DRM_ERROR("Failed to resume queue\n"); + return ret; + } + + queue->queue_active = true; + return 0; } const struct amdgpu_userq_funcs userq_mes_v11_0_funcs = { .mqd_create = mes_v11_0_userq_mqd_create, .mqd_destroy = mes_v11_0_userq_mqd_destroy, + .suspend = mes_v11_0_userq_suspend, + .resume = mes_v11_0_userq_resume, }; |
