diff options
| author | David Rosca <[email protected]> | 2025-08-18 07:18:37 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-09-09 20:42:26 +0000 |
| commit | 3318f2d20ce48849855df5e190813826d0bc3653 (patch) | |
| tree | 1309df4c56f165041427a6cc142ed2359fb9451e /drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | |
| parent | drm/amdgpu/vcn4: Fix IB parsing with multiple engine info packages (diff) | |
| download | kernel-3318f2d20ce48849855df5e190813826d0bc3653.tar.gz kernel-3318f2d20ce48849855df5e190813826d0bc3653.zip | |
drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time
There is no reason to require this to happen on first submitted IB only.
We need to wait for the queue to be idle, but it can be done at any
time (including when there are multiple video sessions active).
Signed-off-by: David Rosca <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit 8908fdce0634a623404e9923ed2f536101a39db5)
Cc: [email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 311fb595bd69..706f3b2f484f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1808,15 +1808,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, struct amdgpu_job *job) { struct drm_gpu_scheduler **scheds; - - /* The create msg must be in the first IB submitted */ - if (atomic_read(&job->base.entity->fence_seq)) - return -EINVAL; + struct dma_fence *fence; /* if VCN0 is harvested, we can't support AV1 */ if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) return -EINVAL; + /* wait for all jobs to finish before switching to instance 0 */ + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull); + if (fence) { + dma_fence_wait(fence, false); + dma_fence_put(fence); + } + scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] [AMDGPU_RING_PRIO_0].sched; drm_sched_entity_modify_sched(job->base.entity, scheds, 1); |