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authorFriedrich Vock <[email protected]>2024-01-23 11:52:03 +0000
committerAlex Deucher <[email protected]>2024-01-31 22:39:47 +0000
commit7330256268664ea0a7dd5b07a3fed363093477dd (patch)
tree72e1db9a997df34a6375c4847516763b4bce8bb4 /drivers/gpu/drm/amd/amdgpu/tonga_ih.c
parentdrm/amdgpu: remove asymmetrical irq disabling in vcn 4.0.5 suspend (diff)
downloadkernel-7330256268664ea0a7dd5b07a3fed363093477dd.tar.gz
kernel-7330256268664ea0a7dd5b07a3fed363093477dd.zip
drm/amdgpu: Reset IH OVERFLOW_CLEAR bit
Allows us to detect subsequent IH ring buffer overflows as well. Cc: Joshua Ashton <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: [email protected] Signed-off-by: Friedrich Vock <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/tonga_ih.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 917707bba7f3..450b6e831509 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
+ /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+ * can be detected.
+ */
+ tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+ WREG32(mmIH_RB_CNTL, tmp);
+
out:
return (wptr & ih->ptr_mask);
}