diff options
| author | Alex Jivin <[email protected]> | 2020-06-24 16:41:14 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-07-02 16:02:49 +0000 |
| commit | fb40bceb6cdff19809b2a3fb7fa4bed36d2638bb (patch) | |
| tree | cae6c7e7ec9e5a72ac0e9574a0afed1b0af1e78e /drivers/gpu/drm/amd/amdgpu/sid.h | |
| parent | drm/amdgpu: SI support for UVD clock control (diff) | |
| download | kernel-fb40bceb6cdff19809b2a3fb7fa4bed36d2638bb.tar.gz kernel-fb40bceb6cdff19809b2a3fb7fa4bed36d2638bb.zip | |
drm/amdgpu: SI support for VCE clock control
Port functionality from the Radeon driver to support
VCE clock control.
Signed-off-by: Alex Jivin <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sid.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sid.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h index 262da0fc8b2e..b3e2dbaf7bd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sid.h +++ b/drivers/gpu/drm/amd/amdgpu/sid.h @@ -2461,4 +2461,36 @@ #define MC_VM_FB_OFFSET 0x81a +/* Discrete VCE clocks */ +#define CG_VCEPLL_FUNC_CNTL 0xc0030600 +#define VCEPLL_RESET_MASK 0x00000001 +#define VCEPLL_SLEEP_MASK 0x00000002 +#define VCEPLL_BYPASS_EN_MASK 0x00000004 +#define VCEPLL_CTLREQ_MASK 0x00000008 +#define VCEPLL_VCO_MODE_MASK 0x00000600 +#define VCEPLL_REF_DIV_MASK 0x003F0000 +#define VCEPLL_CTLACK_MASK 0x40000000 +#define VCEPLL_CTLACK2_MASK 0x80000000 + +#define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 +#define VCEPLL_PDIV_A(x) ((x) << 0) +#define VCEPLL_PDIV_A_MASK 0x0000007F +#define VCEPLL_PDIV_B(x) ((x) << 8) +#define VCEPLL_PDIV_B_MASK 0x00007F00 +#define EVCLK_SRC_SEL(x) ((x) << 20) +#define EVCLK_SRC_SEL_MASK 0x01F00000 +#define ECCLK_SRC_SEL(x) ((x) << 25) +#define ECCLK_SRC_SEL_MASK 0x3E000000 + +#define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 +#define VCEPLL_FB_DIV(x) ((x) << 0) +#define VCEPLL_FB_DIV_MASK 0x01FFFFFF + +#define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 + +#define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 +#define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 +#define VCEPLL_SSEN_MASK 0x00000001 + + #endif |