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| author | Alex Deucher <[email protected]> | 2020-08-18 23:24:03 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-08-26 20:40:18 +0000 |
| commit | f8646661f713fb7d33ebe404d418bd3fa55c383e (patch) | |
| tree | 473f046a55f7336acdf0950ae8956bb8424d8441 /drivers/gpu/drm/amd/amdgpu/si.c | |
| parent | drm/amd/display: Add DPCS regs for dcn3 link encoder (diff) | |
| download | kernel-f8646661f713fb7d33ebe404d418bd3fa55c383e.tar.gz kernel-f8646661f713fb7d33ebe404d418bd3fa55c383e.zip | |
drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it. It's also DCN, not DCE, so remove it from the
DCE12 header.
No functional change.
Acked-by: Nirmoy Das <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si.c')
0 files changed, 0 insertions, 0 deletions