diff options
| author | Sathishkumar S <[email protected]> | 2025-02-26 10:29:47 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-03-05 15:47:36 +0000 |
| commit | a29936bcd21eea7ac87546e2107313cd0f62c4d7 (patch) | |
| tree | 416b26df4c236ef8b45da9fe30a0b0ecfdfe4a39 /drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | |
| parent | drm/amdkfd: flag per-sdma queue reset supported to user space (diff) | |
| download | kernel-a29936bcd21eea7ac87546e2107313cd0f62c4d7.tar.gz kernel-a29936bcd21eea7ac87546e2107313cd0f62c4d7.zip | |
drm/amdgpu: Fix core reset sequence for JPEG5_0_1
For cores 1 through 9 repair the core reset sequence by
adjusting offsets to access the expected registers.
Signed-off-by: Sathishkumar S <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 56c01d207e20..218e16b68f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -672,24 +672,20 @@ static void jpeg_v5_0_1_core_stall_reset(struct amdgpu_ring *ring) WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_UVD_JMI_CLIENT_STALL, reg_offset, 0x1F); - SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, - regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, - 0x1F, 0x1F); + SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, + reg_offset, 0x1F, 0x1F); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_JPEG_LMI_DROP, reg_offset, 0x1F); - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, - regJPEG_CORE_RST_CTRL, - reg_offset, 1 << ring->pipe); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_UVD_JMI_CLIENT_STALL, reg_offset, 0x00); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_JPEG_LMI_DROP, reg_offset, 0x00); - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, - regJPEG_CORE_RST_CTRL, - reg_offset, 0x00); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); } static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) |