diff options
| author | Bob Zhou <[email protected]> | 2024-06-04 07:08:29 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-14 20:15:59 +0000 |
| commit | 37f432481d6ba2077eff1b988b58a18fa87831b7 (patch) | |
| tree | 1aa159ded8b6b286f0a06776c5652f3eefcbd24c /drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | |
| parent | drm/amdgpu: add lock in amdgpu_gart_invalidate_tlb (diff) | |
| download | kernel-37f432481d6ba2077eff1b988b58a18fa87831b7.tar.gz kernel-37f432481d6ba2077eff1b988b58a18fa87831b7.zip | |
drm/amdgpu: fix the overflowed constant warning for RREG32_SOC15()
To fix potential overflowed constant warning reported by Coverity,
modify the variables to uint32_t.
Signed-off-by: Bob Zhou <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/imu_v12_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c index 0c8ef908d112..6ff9cf27059a 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c @@ -119,7 +119,8 @@ static int imu_v12_0_load_microcode(struct amdgpu_device *adev) static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) { - int i, imu_reg_val = 0; + u32 imu_reg_val = 0; + int i; for (i = 0; i < adev->usec_timeout; i++) { imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); @@ -138,7 +139,7 @@ static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) static void imu_v12_0_setup(struct amdgpu_device *adev) { - int imu_reg_val; + u32 imu_reg_val; WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); @@ -157,7 +158,7 @@ static void imu_v12_0_setup(struct amdgpu_device *adev) static int imu_v12_0_start(struct amdgpu_device *adev) { - int imu_reg_val; + u32 imu_reg_val; imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); imu_reg_val &= 0xfffffffe; |