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authorVictor Lu <[email protected]>2025-02-13 23:41:26 +0000
committerAlex Deucher <[email protected]>2025-03-07 17:52:29 +0000
commit3646cc65e2747ff112d7de1a05a2e756414b771e (patch)
tree78ee4de087f8557aa32e763763eca02d65194c43 /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
parentdrm/amdgpu: Fix core reset sequence for JPEG5_0_1 (diff)
downloadkernel-3646cc65e2747ff112d7de1a05a2e756414b771e.tar.gz
kernel-3646cc65e2747ff112d7de1a05a2e756414b771e.zip
drm/amdgpu: Do not write to GRBM_CNTL if Aldebaran SRIOV
Aldebaran SRIOV VF does not have write permissions to GRBM_CTNL. This access can be skipped to avoid a dmesg warning. v2: Use GC IP version check instead of asic check Signed-off-by: Victor Lu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f7938d318f26..1f0f03108a82 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2637,7 +2637,10 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
u32 tmp;
int i;
- WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
+ if (!amdgpu_sriov_vf(adev) ||
+ amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) {
+ WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
+ }
gfx_v9_0_tiling_mode_table_init(adev);