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| author | Jani Nikula <[email protected]> | 2024-06-19 08:38:31 +0000 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2024-06-19 08:38:31 +0000 |
| commit | d754ed2821fd9675d203cb73c4afcd593e28b7d0 (patch) | |
| tree | cd16683cd956a7c334d7e1b3baf02e2e7baa729c /drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |
| parent | intel_alpm: Fix wrong offset for PORT_ALPM_* registers (diff) | |
| parent | Merge tag 'amd-drm-next-6.11-2024-06-07' of https://gitlab.freedesktop.org/ag... (diff) | |
| download | kernel-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.gz kernel-d754ed2821fd9675d203cb73c4afcd593e28b7d0.zip | |
Merge drm/drm-next into drm-intel-next
Sync to v6.10-rc3.
Signed-off-by: Jani Nikula <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 541dbd70d8c7..8f19b6ae8d5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -963,8 +963,6 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); - if (err) - goto out; out: if (err) { pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); @@ -2757,44 +2755,6 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) return 0; } -struct hqd_registers { - u32 cp_mqd_base_addr; - u32 cp_mqd_base_addr_hi; - u32 cp_hqd_active; - u32 cp_hqd_vmid; - u32 cp_hqd_persistent_state; - u32 cp_hqd_pipe_priority; - u32 cp_hqd_queue_priority; - u32 cp_hqd_quantum; - u32 cp_hqd_pq_base; - u32 cp_hqd_pq_base_hi; - u32 cp_hqd_pq_rptr; - u32 cp_hqd_pq_rptr_report_addr; - u32 cp_hqd_pq_rptr_report_addr_hi; - u32 cp_hqd_pq_wptr_poll_addr; - u32 cp_hqd_pq_wptr_poll_addr_hi; - u32 cp_hqd_pq_doorbell_control; - u32 cp_hqd_pq_wptr; - u32 cp_hqd_pq_control; - u32 cp_hqd_ib_base_addr; - u32 cp_hqd_ib_base_addr_hi; - u32 cp_hqd_ib_rptr; - u32 cp_hqd_ib_control; - u32 cp_hqd_iq_timer; - u32 cp_hqd_iq_rptr; - u32 cp_hqd_dequeue_request; - u32 cp_hqd_dma_offload; - u32 cp_hqd_sema_cmd; - u32 cp_hqd_msg_type; - u32 cp_hqd_atomic0_preop_lo; - u32 cp_hqd_atomic0_preop_hi; - u32 cp_hqd_atomic1_preop_lo; - u32 cp_hqd_atomic1_preop_hi; - u32 cp_hqd_hq_scheduler0; - u32 cp_hqd_hq_scheduler1; - u32 cp_mqd_control; -}; - static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, int mec, int pipe) { |