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authorSomalapuram Amaranath <[email protected]>2024-10-10 18:08:06 +0000
committerAlex Deucher <[email protected]>2025-04-08 20:48:19 +0000
commit988c9e704670a39ef2fd23f3eeb2d3b9c813dab1 (patch)
tree8cf2e209909d984a4a1069c7fddd2acb8717cecf /drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
parentdrm/amdgpu/uq: make MES UQ setup generic (diff)
downloadkernel-988c9e704670a39ef2fd23f3eeb2d3b9c813dab1.tar.gz
kernel-988c9e704670a39ef2fd23f3eeb2d3b9c813dab1.zip
drm/amdgpu: enable userqueue support for GFX12
This patch enables Usermode queue support across GFX, Compute and SDMA IPs on GFX12/SDMA7. It typically reuses Navi3X userqueue IP functions to create and destroy MQDs. v2: rebase on proposed changes (Alex) Cc: Alex Deucher <[email protected]> Cc: Christian Koenig <[email protected]> Cc: Arvind Yadav <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Somalapuram Amaranath <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 8b409b4a1cb3..ee65f4057872 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -44,6 +44,7 @@
#include "gfx_v12_0.h"
#include "nbif_v6_3_1.h"
#include "mes_v12_0.h"
+#include "mes_userqueue.h"
#define GFX12_NUM_GFX_RINGS 1
#define GFX12_MEC_HPD_SIZE 2048
@@ -1417,6 +1418,10 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 2;
adev->gfx.mec.num_queue_per_pipe = 4;
+#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
+ adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+#endif
break;
default:
adev->gfx.me.num_me = 1;