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authorPrike Liang <[email protected]>2024-11-15 08:04:48 +0000
committerAlex Deucher <[email protected]>2024-12-10 15:26:45 +0000
commit66f4f7d5aa316f88b0fcb5c2e2b80014da28f640 (patch)
tree672a0844ec3888d4772df81d758bf954558e18bb /drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
parentdrm/amdgpu/sdma4.4.2: implement ring reset callback for sdma4.4.2 (diff)
downloadkernel-66f4f7d5aa316f88b0fcb5c2e2b80014da28f640.tar.gz
kernel-66f4f7d5aa316f88b0fcb5c2e2b80014da28f640.zip
drm/amdgpu: reduce the mmio writes in kiq setting
There's no need to perform the two MMIO writes in the KIQ Setting registers programmed period, and reducing the MMIO writes will save the driver loading time. Signed-off-by: Prike Liang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index fe7c48f2fb2a..8a8b55c332c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -2832,9 +2832,7 @@ static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
- WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
- tmp |= 0x80;
- WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
+ WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
}
static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)