diff options
| author | Wayne Lin <[email protected]> | 2021-03-10 15:40:01 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-03-24 03:36:31 +0000 |
| commit | d1fa15680913ca1334fc2e8de6aa8e74fcfb78c6 (patch) | |
| tree | 4c81df5bcf57192e4f414085105a0f796ff8713d /drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | |
| parent | drm/amd/display: Fix vertical interrupt 0 registering issue (diff) | |
| download | kernel-d1fa15680913ca1334fc2e8de6aa8e74fcfb78c6.tar.gz kernel-d1fa15680913ca1334fc2e8de6aa8e74fcfb78c6.zip | |
drm/amd/display: Support vertical interrupt 0 for all dcn ASIC
[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.
Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and
cause pointer errors.
[How]
Add support of vertical interrupt 0 for all dcn ASIC.
v2: squash in build fix (Alex)
Signed-off-by: Wayne Lin <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Acked-by: Solomon Chiu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c')
0 files changed, 0 insertions, 0 deletions