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authorShane Xiao <[email protected]>2024-05-29 09:57:31 +0000
committerAlex Deucher <[email protected]>2024-06-05 15:02:43 +0000
commit392829010238319689ee7aab5f9acffc23a53899 (patch)
treeb206862bb909204dba1aca85f2dd89acf50b4647 /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
parentdrm/amdgpu: disable lane0 L1TLB and enable lane1 L1TLB (diff)
downloadkernel-392829010238319689ee7aab5f9acffc23a53899.tar.gz
kernel-392829010238319689ee7aab5f9acffc23a53899.zip
drm/amdgpu: Update the impelmentation of AMDGPU_PTE_MTYPE_NV10
This patch changes the implementation of AMDGPU_PTE_MTYPE_NV10, clear the bits before setting the new one. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: longlyao <[email protected]> Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index acd1b55b8b0e..8019f0d14a8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -108,8 +108,11 @@ struct amdgpu_mem_stats;
| AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
/* gfx10 */
-#define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
-#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
+#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48)
+#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)
+#define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \
+ (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \
+ AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))
/* gfx12 */
#define AMDGPU_PTE_PRT_GFX12 (1ULL << 56)