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| author | Michael Walle <[email protected]> | 2022-03-18 20:13:24 +0000 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2022-03-22 05:33:02 +0000 |
| commit | 74529db3e01d6120f4a6212acac62d29a7faecc2 (patch) | |
| tree | 320e722128651ad2b3744acc810f21fab2233cfc /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |
| parent | net: mdio: mscc-miim: replace magic numbers for the bus reset (diff) | |
| download | kernel-74529db3e01d6120f4a6212acac62d29a7faecc2.tar.gz kernel-74529db3e01d6120f4a6212acac62d29a7faecc2.zip | |
net: mdio: mscc-miim: add lan966x internal phy reset support
The LAN966x has two internal PHYs which are in reset by default. The
driver already supported the internal PHYs of the SparX-5. Now add
support for the LAN966x, too. Add a new compatible to distinguish them.
The LAN966x has additional control bits in this register, thus convert
the regmap_write() to regmap_update_bits() to leave the remaining bits
untouched. This doesn't change anything for the SparX-5 SoC, because
there, the register consists only of reset bits.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c')
0 files changed, 0 insertions, 0 deletions