diff options
| author | Archit Taneja <[email protected]> | 2017-10-27 10:57:30 +0000 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2017-10-28 18:02:58 +0000 |
| commit | b14892801078085cb54dcbe3389057e12c1746a2 (patch) | |
| tree | 6919e77760875f57b8e3817f23513646d4658209 /drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | |
| parent | drm/msm/mdp5: Prepare mdp5_pipe_assign for some rework (diff) | |
| download | kernel-b14892801078085cb54dcbe3389057e12c1746a2.tar.gz kernel-b14892801078085cb54dcbe3389057e12c1746a2.zip | |
drm/msm/mdp5: Update mdp5_pipe_assign to spit out both planes
We currently call mdp5_pipe_assign() twice to assign the left and right
hwpipes for our drm_plane. When merging 2 hwpipes, there are a few
constraints that we need to keep in mind:
- Only the same types of SSPPs are preferred. I.e, a RGB pipe should
be paired with another RGB pipe, VIG with VIG etc.
- The hwpipe staged on the left should have a higher priority than
the hwpipe staged on the right. The priorities are as follows:
VIG0 > VIG1 > VIG2 > VIG3
RGB0 > RGB1 > RGB2 > RGB3
DMA0 > DMA1
We can't apply these constraints easily if mdp5_pipe_assign() is
called twice. Update mdp5_pipe_assign() to find both hwpipes in
one go, and add the extra constraints needed.
Signed-off-by: Archit Taneja <[email protected]>
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c')
0 files changed, 0 insertions, 0 deletions