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| author | Likun Gao <[email protected]> | 2022-04-12 20:57:45 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-05-04 14:43:54 +0000 |
| commit | aca670e41f9fe52176040553f174d517cbd69da9 (patch) | |
| tree | f7849140a346ee01cca698324aebfe6200984b87 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | |
| parent | drm/amd/amdgpu: add more fw load type to fit new ASICs (diff) | |
| download | kernel-aca670e41f9fe52176040553f174d517cbd69da9.tar.gz kernel-aca670e41f9fe52176040553f174d517cbd69da9.zip | |
drm/amdgpu: fix the fw size for sdma
For SDMA, if use the total size of SDMA TH0 and TH1 to allocate fw BO
may result to the ucode data overflow when copy ucode to BO as the PAGE
alignment.
IMU have the same issue.
Fix the above issue by alignment the fw size per fw ID.
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h')
0 files changed, 0 insertions, 0 deletions