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| author | Esben Haabendal <[email protected]> | 2019-04-30 07:17:59 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2019-05-01 18:33:31 +0000 |
| commit | 73f7375d3ed6ad372f1e9404007a0c866063d773 (patch) | |
| tree | b8b355013ec19637c6f26d2686e6975b877c5942 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | net: ll_temac: Allow configuration of IRQ coalescing (diff) | |
| download | kernel-73f7375d3ed6ad372f1e9404007a0c866063d773.tar.gz kernel-73f7375d3ed6ad372f1e9404007a0c866063d773.zip | |
net: ll_temac: Enable DMA when ready, not before
As soon as TAILDESCR_PTR is written, DMA transfers might start.
Let's ensure we are ready to receive DMA IRQ's before doing that.
Signed-off-by: Esben Haabendal <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
0 files changed, 0 insertions, 0 deletions