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| author | Eryk Brol <[email protected]> | 2020-06-19 18:42:09 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-08-17 18:08:34 +0000 |
| commit | bcc6aa61c82d4f12df3ecc884a9eef9d566edae9 (patch) | |
| tree | 7b5df12ff642e55f89fe0a7dbb2cfc98e255eb77 /drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | |
| parent | drm/amd/display: fix dcn3 wide timing dsc validation (diff) | |
| download | kernel-bcc6aa61c82d4f12df3ecc884a9eef9d566edae9.tar.gz kernel-bcc6aa61c82d4f12df3ecc884a9eef9d566edae9.zip | |
drm/amd/display: Fix DSC force enable on SST
[why]
Previously when force enabling DSC on SST display we unknowingly
supressed lane count, which caused DSC to be enabled automatically.
[how]
By adding an additional flag to force enable DSC in dc_dsc.c DSC can
always be enabled with debugfs dsc_clock_en forced to 1
Cc: [email protected]
Signed-off-by: Eryk Brol <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c')
0 files changed, 0 insertions, 0 deletions