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| author | Paul Hsieh <[email protected]> | 2022-11-24 05:03:26 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-12-06 15:16:24 +0000 |
| commit | 8747075f54fa0c5d30fcc48e5149c19c02641fa8 (patch) | |
| tree | 48ce7caf8d59d400f16e7e7b3fa0c3092d59644c /drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | |
| parent | drm/amd/display: Bypass DET swath fill check for max clocks (diff) | |
| download | kernel-8747075f54fa0c5d30fcc48e5149c19c02641fa8.tar.gz kernel-8747075f54fa0c5d30fcc48e5149c19c02641fa8.zip | |
drm/amd/display: read invalid ddc pin status cause engine busy
[Why]
There is no DDC_6 pin on new asic cause the mapping table is
incorrect. When app try to access DDC_VGA port, driver read
an invalid ddc pin status and report engine busy.
[How]
Add dummy DDC_6 pin to align gpio structure.
Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Stylon Wang <[email protected]>
Signed-off-by: Paul Hsieh <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c')
0 files changed, 0 insertions, 0 deletions