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| author | Zhi Wang <[email protected]> | 2016-06-16 12:07:02 +0000 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2016-06-17 19:35:26 +0000 |
| commit | c01fc5322956eb03fd4d1fe2251f037ace890172 (patch) | |
| tree | 2100da22656aa9d45172b1fc2b94cc0cddb2dbf8 /drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | |
| parent | drm/i915: Make ring buffer size of a LRC context configurable (diff) | |
| download | kernel-c01fc5322956eb03fd4d1fe2251f037ace890172.tar.gz kernel-c01fc5322956eb03fd4d1fe2251f037ace890172.zip | |
drm/i915: Make addressing mode bits in context descriptor configurable
Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.
GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a LRC context should be configurable under this case.
v10:
- Fix the identation. (Joonas)
v9:
- Rename the data member in struct i915_gem_context. (Chris)
v8:
- Rename the data member in struct i915_gem_context. (Chris)
v7:
- Move context addressing mode bit into i915_reg.h. (Joonas/Chris)
- Add prefix "INTEL_" for related definitions. (Joonas)
v6:
- Directly save the addressing mode bits inside i915_gem_context. (Chris)
- Move the LRC context addressing mode bits into intel_lrc.h. (Chris)
v5:
- Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
Reviewed-by: Joonas Lahtinen <[email protected]> (v9)
Cc: Joonas Lahtinen <[email protected]>
Cc: Chris Wilson <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Signed-off-by: Zhi Wang <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c')
0 files changed, 0 insertions, 0 deletions