clk: mmp: pxa168: fix incorrect parent clocks

The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
match the information provided by the PXA168 datasheet:

- The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first
  mux option was being calculated as 117 MHz, confirmed on hardware to
  be incorrect.

- The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz
  and 52 MHz were swapped. 78 MHz wasn't listed as an option.

- The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being
  calculated as 312 MHz or 52 MHz.

- The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being
  calculated as 312 MHz or 52 MHz.

Signed-off-by: Doug Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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