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authorAlvin Lee <[email protected]>2024-04-26 21:14:19 +0000
committerAlex Deucher <[email protected]>2024-06-05 15:06:28 +0000
commit4621e10e0158941d44223fd5f7451312473f73da (patch)
treea0a2cf899a8d0117593fe4dbffdd6d8ffe19ca6b /drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
parentdrm/amd/display: Add retires when read DPCD (diff)
downloadkernel-4621e10e0158941d44223fd5f7451312473f73da.tar.gz
kernel-4621e10e0158941d44223fd5f7451312473f73da.zip
drm/amd/display: Only program P-State force if pipe config changed
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by: Samson Tam <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c')
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