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| author | Luben Tuikov <[email protected]> | 2021-07-02 23:58:42 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-07-08 19:12:51 +0000 |
| commit | c0838d3a93fc5e51b4a9654f53f499da1778dad8 (patch) | |
| tree | c768cb17e118cf6651a08e19bd75e515e83acd77 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | |
| parent | drm/amd/pm: Add I2C quirk table to Aldebaran (diff) | |
| download | kernel-c0838d3a93fc5e51b4a9654f53f499da1778dad8.tar.gz kernel-c0838d3a93fc5e51b4a9654f53f499da1778dad8.zip | |
drm/amdgpu: The I2C IP doesn't support 0 writes/reads
The I2C IP doesn't support writes or reads of 0 bytes.
In order for a START/STOP transaction to take
place on the bus, the data written/read has to be
at least one byte.
That is, you cannot generate a write with 0 bytes,
just to get the ACK from a device, just so you can
probe that device if it is on the bus and so to
discover all devices on the bus--you'll have to
read at least one byte. Writes of 0 bytes generate
no START/STOP on this I2C IP--the bus is not
engaged at all.
Set the I2C_AQ_NO_ZERO_LEN to the existing I2C
quirk tables for Aldebaran, Arcturus, Navi10 and
Sienna Cichlid, and add a quirk table to the I2C
driver which drives the bus when the SMU
doesn't--for instance on Vega20.
Cc: Alexander Deucher <[email protected]>
Cc: Andrey Grodzovsky <[email protected]>
Cc: Lijo Lazar <[email protected]>
Cc: John Clements <[email protected]>
Cc: Hawking Zhang <[email protected]>
Signed-off-by: Luben Tuikov <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h')
0 files changed, 0 insertions, 0 deletions
