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| author | Joshua Aberback <[email protected]> | 2025-01-08 17:03:23 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-02-13 02:02:57 +0000 |
| commit | 3a7810c212bcf2f722671dadf4b23ff70a7d23ee (patch) | |
| tree | 8006766126c618a4c69a8caf84e24ee2d4b7aec2 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | drm/amd/display: Use Nominal vBlank If Provided Instead Of Capping It (diff) | |
| download | kernel-3a7810c212bcf2f722671dadf4b23ff70a7d23ee.tar.gz kernel-3a7810c212bcf2f722671dadf4b23ff70a7d23ee.zip | |
drm/amd/display: Increase block_sequence array size
[Why]
It's possible to generate more than 50 steps in hwss_build_fast_sequence,
for example with a 6-pipe asic where all pipes are in one MPC chain. This
overflows the block_sequence buffer and corrupts block_sequence_steps,
causing a crash.
[How]
Expand block_sequence to 100 items. A naive upper bound on the possible
number of steps for a 6-pipe asic, ignoring the potential for steps to be
mutually exclusive, is 91 with current code, therefore 100 is sufficient.
Reviewed-by: Alvin Lee <[email protected]>
Signed-off-by: Joshua Aberback <[email protected]>
Signed-off-by: Wayne Lin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions