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| author | Yang Wang <[email protected]> | 2022-09-09 03:06:50 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-09-13 16:56:16 +0000 |
| commit | cd3a49af58c23dd5ffa1d4d5a120ee2354d2e8d8 (patch) | |
| tree | 88c4ee7019cc15b86adaa54063d806c6265959c9 /drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | |
| parent | drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0 (diff) | |
| download | kernel-cd3a49af58c23dd5ffa1d4d5a120ee2354d2e8d8.tar.gz kernel-cd3a49af58c23dd5ffa1d4d5a120ee2354d2e8d8.zip | |
drm/amdgpu: change the alignment size of TMR BO to 1M
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
v2:
add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size
Signed-off-by: Yang Wang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index c32b74bd970f..e593e8c2a54d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -36,6 +36,7 @@ #define PSP_CMD_BUFFER_SIZE 0x1000 #define PSP_1_MEG 0x100000 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) +#define PSP_TMR_ALIGNMENT 0x100000 #define PSP_FW_NAME_LEN 0x24 enum psp_shared_mem_size { |