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authorLi Ming <[email protected]>2025-03-23 09:31:09 +0000
committerDave Jiang <[email protected]>2025-04-09 19:48:18 +0000
commit6af941db6a60a27209bdb2da1a3a780574d617fe (patch)
treef1dd8b319030574e3ee80f20d1355a5648c2ac90 /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
parentcxl/core: Fix caching dport GPF DVSEC issue (diff)
downloadkernel-6af941db6a60a27209bdb2da1a3a780574d617fe.tar.gz
kernel-6af941db6a60a27209bdb2da1a3a780574d617fe.zip
cxl/pci: Update Port GPF timeout only when the first EP attaching
update_gpf_port_dvsec() is used to update GPF Phase timeout, if a CXL switch is under a CXL root port, update_gpf_port_dvsec() will be invoked on the CXL root port when each cxl memory device under the CXL switch is attaching. It is enough to be invoked once, others are redundant. When the first EP attaching, it always triggers its ancestor dports to locate their own Port GPF DVSEC. The change is that invoking update_gpf_port_dvsec() on these ancestor dports after ancestor dport locating a Port GPF DVSEC. It guarantees that update_gpf_port_dvsec() is invoked on a dport only happens during the first EP attaching. Signed-off-by: Li Ming <[email protected]> Reviewed-by: Davidlohr Bueso <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Reviewed-by: Dan Williams <[email protected]> Tested-by: Davidlohr Bueso <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Dave Jiang <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
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