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| author | Nicholas Kazlauskas <[email protected]> | 2024-07-16 21:41:54 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-07-27 21:34:07 +0000 |
| commit | bd870cfd21489d28195fda157710ebd4cecaa8ca (patch) | |
| tree | 2f58ea6f7e4708018a1f0956c692818a80030cdf /drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | |
| parent | drm/amd/display: Reset VRR config during resume (diff) | |
| download | kernel-bd870cfd21489d28195fda157710ebd4cecaa8ca.tar.gz kernel-bd870cfd21489d28195fda157710ebd4cecaa8ca.zip | |
drm/amd/display: Add seamless boot support for more DIG operation modes
[Why]
When pre-OS firmware enables display support for displays that operate
the DIG in 2 pixels per cycle processing modes the inferred pixel rate
from get_pixel_clk_frequency_100hz does not account for the true pixel
rate since we're outputting 2 per cycle past the stream encoder.
This causes seamless boot validation to abort early.
[How]
Add a new stream encoder function for getting pixels per cycle from the
stream encoder. If the pixels per cycle is greater than 1 and the driver
policy is to enable 2 pixels per cycle for post-OS then allow seamless
boot to continue.
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Reviewed-by: Duncan Ma <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h')
0 files changed, 0 insertions, 0 deletions