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| author | Joshua Aberback <[email protected]> | 2021-02-27 00:44:24 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-03-24 03:03:12 +0000 |
| commit | 554ba183b135ef09250b61a202d88512b5bbd03a (patch) | |
| tree | 5ef166efdf619de5b5acc01b466bc10ca312c61c /drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | |
| parent | drm/amd/display: Revert dram_clock_change_latency for DCN2.1 (diff) | |
| download | kernel-554ba183b135ef09250b61a202d88512b5bbd03a.tar.gz kernel-554ba183b135ef09250b61a202d88512b5bbd03a.zip | |
drm/amd/display: Align cursor cache address to 2KB
[Why]
The registers for the address of the cursor are aligned to 2KB, so all
cursor surfaces also need to be aligned to 2KB. Currently, the
provided cursor cache surface is not aligned, so we need a workaround
until alignment is enforced by the surface provider.
[How]
- round up surface address to nearest multiple of 2048
- current policy is to provide a much bigger cache size than
necessary,so this operation is safe
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Joshua Aberback <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h')
0 files changed, 0 insertions, 0 deletions