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authorAlex Deucher <[email protected]>2025-03-19 14:03:31 +0000
committerAlex Deucher <[email protected]>2025-03-21 16:16:35 +0000
commit5e93d0e335e992066cf394c00808ee192da4ecf5 (patch)
tree78c58a7d4550fcf6bc5a5366a6cf27f04a301b0b /drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
parentdrm/amdgpu/mes: enable compute pipes across all MEC (diff)
downloadkernel-5e93d0e335e992066cf394c00808ee192da4ecf5.tar.gz
kernel-5e93d0e335e992066cf394c00808ee192da4ecf5.zip
drm/amdgpu/mes: clean up SDMA HQD loop
Follow the same logic as the other IP types. Reviewed-by: Prike Liang <[email protected]> Acked-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 230d0d05c65e..85f774063f9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -154,11 +154,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
- /* zero sdma_hqd_mask for non-existent engine */
- if (adev->sdma.num_instances == 1)
- adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
- else
- adev->mes.sdma_hqd_mask[i] = 0xfc;
+ if (i >= adev->sdma.num_instances)
+ break;
+ adev->mes.sdma_hqd_mask[i] = 0xfc;
}
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {