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| author | Thomas Gleixner <[email protected]> | 2024-12-10 10:20:43 +0000 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2025-01-15 09:56:21 +0000 |
| commit | 8d187a77f04c14fb459a5301d69f733a5a1396bc (patch) | |
| tree | 592aadd15d78c3e91ea7ee541b31752d4c9fcdc8 /drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | |
| parent | irqchip/loongarch-avec: Add multi-nodes topology support (diff) | |
| download | kernel-8d187a77f04c14fb459a5301d69f733a5a1396bc.tar.gz kernel-8d187a77f04c14fb459a5301d69f733a5a1396bc.zip | |
genirq: Make handle_enforce_irqctx() unconditionally available
Commit 1b57d91b969c ("irqchip/gic-v2, v3: Prevent SW resends entirely")
sett the flag which enforces interrupt handling in interrupt context and
prevents software base resends for ARM GIC v2/v3.
But it missed that the helper function which checks the flag was hidden
behind CONFIG_GENERIC_PENDING_IRQ, which is not set by ARM[64].
Make the helper unconditionally available so that the enforcement actually
works.
Fixes: 1b57d91b969c ("irqchip/gic-v2, v3: Prevent SW resends entirely")
Signed-off-by: Thomas Gleixner <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c')
0 files changed, 0 insertions, 0 deletions