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authorSamuel Zhang <[email protected]>2025-05-08 06:36:35 +0000
committerAlex Deucher <[email protected]>2025-06-18 16:19:15 +0000
commit4108c2be12ebe78accb40d43f4713a7cc481b18a (patch)
treec3c8e9f0679ee0968f0262d9cb43418b7aa2413e /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
parentdrm/amdgpu: enable pdb0 for hibernation on SRIOV (diff)
downloadkernel-4108c2be12ebe78accb40d43f4713a7cc481b18a.tar.gz
kernel-4108c2be12ebe78accb40d43f4713a7cc481b18a.zip
drm/amdgpu: fix fence fallback timer expired error
IH is not working after switching a new gpu index for the first time. During VM resume, QEMU programming of VF MSIX table (register GFXMSIX_VECT0_ADDR_LO) may not work.The access could be blocked by nBIF protection as VF isn't in exclusive access mode. Exclusive access is enabled now, disable/enable MSIX so that QEMU reprograms MSIX table. call amdgpu_restore_msix on resume to restore msix table. Signed-off-by: Samuel Zhang <[email protected]> Acked-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index 04c0b4fa17a4..9f0417456abd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -146,5 +146,6 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
int amdgpu_irq_add_domain(struct amdgpu_device *adev);
void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
+void amdgpu_restore_msix(struct amdgpu_device *adev);
#endif