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| author | John Madieu <[email protected]> | 2025-07-02 00:57:03 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2025-07-08 09:36:16 +0000 |
| commit | e6e54229f328c30a1b4ecba1253f9d314dd42e33 (patch) | |
| tree | 44cb40af39a0ba2cabc23fe5142d629316607f1a /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
| parent | clk: renesas: r9a09g057: Add XSPI clock/reset (diff) | |
| download | kernel-e6e54229f328c30a1b4ecba1253f9d314dd42e33.tar.gz kernel-e6e54229f328c30a1b4ecba1253f9d314dd42e33.zip | |
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.
Reviewed-by: Biju Das <[email protected]>
Signed-off-by: John Madieu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions