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| author | Chris Wilson <[email protected]> | 2017-06-15 13:11:29 +0000 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2017-06-19 07:52:34 +0000 |
| commit | a21ef715fbb8210c50b1d684145f8acdf2339596 (patch) | |
| tree | e7388adfc2badadf42b5fe1220e77f4d3b635422 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
| parent | drm/i915: Fix GVT-g PVINFO version compatibility check (diff) | |
| download | kernel-a21ef715fbb8210c50b1d684145f8acdf2339596.tar.gz kernel-a21ef715fbb8210c50b1d684145f8acdf2339596.zip | |
drm/i915: Differentiate between sw write location into ring and last hw read
We need to keep track of the last location we ask the hw to read up to
(RING_TAIL) separately from our last write location into the ring, so
that in the event of a GPU reset we do not tell the HW to proceed into
a partially written request (which can happen if that request is waiting
for an external signal before being executed).
v2: Refactor intel_ring_reset() (Mika)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100144
Testcase: igt/gem_exec_fence/await-hang
Fixes: 821ed7df6e2a ("drm/i915: Update reset path to fix incomplete requests")
Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to actual hw submission")
Signed-off-by: Chris Wilson <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Mika Kuoppala <[email protected]>
(cherry picked from commit e6ba9992de6c63fe86c028b4876338e1cb7dac34)
Signed-off-by: Jani Nikula <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions