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| author | Sugar Zhang <[email protected]> | 2021-08-26 04:01:48 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-08-26 12:59:31 +0000 |
| commit | 6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af (patch) | |
| tree | e456bf342072a723076a8b77880a3c2281fbd217 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
| parent | ASoC: rockchip: i2s: Add support for set bclk ratio (diff) | |
| download | kernel-6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af.tar.gz kernel-6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af.zip | |
ASoC: rockchip: i2s: Fixup clk div error
MCLK maybe not precise as required because of PLL,
but which still can be used and no side effect. so,
using DIV_ROUND_CLOSEST instead div.
e.g.
set mclk to 11289600 Hz, but get 11289598 Hz.
Signed-off-by: Sugar Zhang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions